(1) Field
This invention relates generally to flash memory arrays that are used in integrated flash systems or system-on-chip (SOC) microcontroller flash systems. More specifically, this invention relates to load compensation in multilevel flash memory arrays.
(2) Description of Related Information
As information technology progresses at an unprecedented pace, the need for information storage increases proportionately. Accordingly, the non volatile information in stationary or portable communication demands higher capability and capacity storage. One approach to increasing the amount of storage is by decreasing physical dimensions of the stored bit (e.g., memory cell) to smaller dimensions such as nanocell technology. Another approach is to increase the storage density per bit. The second approach is known as digital multilevel nonvolatile storage technology. A sense amplifier reads the content of a memory cell by comparison to reference levels. As more bits are stored in a multilevel memory cell, the voltage separation of reference levels decreases.
Variations in many parameters, such as the magnitude of supply voltage VDD, can result in inaccurate data readings and other errors as voltage separation decreases and corresponding sensitivity to such variations increases. Accordingly, it is often desirable to develop systems and methods of compensating for these variations, so as to reduce fluctuations in the operating parameters of memory arrays and improve the accuracy with which data is written to, or read from, multilevel memory cells.